Verilog 6502 softcore

This is a fairly small 6502 softcore for the ice40 sized FPGAs. The intended purpose is for emulating classic Atari vector games like Battle Zone, although it could be used for other systems that had the same CPU.

There are several quirks in the original 6502 related to zero page addressing and this implements them in order to pass the test. Some were fixed in later chips, so be careful if your emulation target depends on a specific version.

Tests

It passes all of the non-BCD test vectors from https://github.com/SingleStepTests/65x02 for the 6502's register state and RAM (bus cycles are not tested), with the exception of a self modifying JSR that has a stack pointer that points to the middle of the instruction, leading to a overwrite of the next byte in the instruction (and that does not occur in practice).

The BCD tests for ADC pass, with the exception of the N and V flags. According to http://www.6502.org/tutorials/vflag.html these are undefined for the 6502, so the test harness masks them off in the BCD tests.

SBC does not pass BCD tests; it's not clear from http://www.6502.org/tutorials/decimal_mode.html exactly what the results are supposed to be when given values that are not within range. Perhaps it could be fixed up.